{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8536649","patent":{"patent_number":"US-8536649","title":"Method to reduce threshold voltage variability with through gate well implant","assignee":null,"inventors":[],"filing_date":"2012-09-10T00:00:00.000Z","publication_date":"2013-09-17T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L"],"num_claims":20,"abstract":"The present disclosure provides a semiconductor device that may include a substrate including a semiconductor layer overlying an insulating layer. A gate structure that is present on a channel portion of the semiconductor layer. A first dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the first dopant region is present within the lower portion of the gate conductor and the upper portion of the semiconductor layer. A second dopant region is present in the channel portion of the semiconductor layer, in which the peak concentration of the second dopant region is present within the lower portion of the semiconductor layer."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method to reduce threshold voltage variability with through gate well implant","description":"The present disclosure provides a semiconductor device that may include a substrate including a semiconductor layer overlying an insulating layer. A gate structure that is present on a channel portion","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8536649","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8536649","citation_suggestion":"Patentable. \"Method to reduce threshold voltage variability with through gate well implant\" (US-8536649). https://patentable.app/patents/US-8536649","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8536649","json":"https://patentable.app/api/llm-context/US-8536649","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T09:42:44.471Z"}