{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8537586","patent":{"patent_number":"US-8537586","title":"Memory array and storage method","assignee":null,"inventors":[],"filing_date":"2008-07-02T00:00:00.000Z","publication_date":"2013-09-17T00:00:00.000Z","cpc_codes":["G11C","G11C"],"num_claims":13,"abstract":"A memory arrangement comprises a first memory transistor (11) for non-volatile storage of a first bit, a second memory transistor (17) for non-volatile storage of the first bit in inverted form, and a word line (29) that is connected to a control terminal (12) of the first memory transistor (11) and a control terminal (18) of the second memory transistor (17). The memory arrangement further comprises a read amplifier (23) with a first input (24) that is coupled to the first memory transistor (11) for supplying a first bit line signal (BL1), a second input (25) that is coupled to the second memory transistor (17) for supplying a second bit line signal (BL2), and an output (26) for provision of an output signal (SOUT) as a function of the first bit line signal (BL1) and the second bit line signal (BL2)."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory array and storage method","description":"A memory arrangement comprises a first memory transistor (11) for non-volatile storage of a first bit, a second memory transistor (17) for non-volatile storage of the first bit in inverted form, and a","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8537586","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8537586","citation_suggestion":"Patentable. \"Memory array and storage method\" (US-8537586). https://patentable.app/patents/US-8537586","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8537586","json":"https://patentable.app/api/llm-context/US-8537586","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T14:05:37.480Z"}