{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8537601","patent":{"patent_number":"US-8537601","title":"Memory controller with selective data transmission delay","assignee":null,"inventors":[],"filing_date":"2012-07-06T00:00:00.000Z","publication_date":"2013-09-17T00:00:00.000Z","cpc_codes":["G06F","G11C","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":18,"abstract":"A DRAM controller component generates a timing signal and transmits, to a DRAM, write data that requires a first time interval to propagate from the DRAM controller component to the DRAM and to be sampled by the DRAM on one or more edges of the timing signal, a clock signal that requires a second time interval to propagate from the DRAM controller component to the DRAM, and a write command, associated with the write data, to be sampled by the DRAM on one or more edges of the clock signal. The DRAM controller component includes series-coupled delay elements to generate respective incrementally delayed signals, and a multiplexer to select one of the delayed signals to time the transmission of the write data, such that transmission of the write data is delayed based on a difference between the first time interval and the second time interval."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory controller with selective data transmission delay","description":"A DRAM controller component generates a timing signal and transmits, to a DRAM, write data that requires a first time interval to propagate from the DRAM controller component to the DRAM and to be sam","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8537601","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8537601","citation_suggestion":"Patentable. \"Memory controller with selective data transmission delay\" (US-8537601). https://patentable.app/patents/US-8537601","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8537601","json":"https://patentable.app/api/llm-context/US-8537601","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T21:21:34.582Z"}