{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8537633","patent":{"patent_number":"US-8537633","title":"Methods of operating DRAM devices having adjustable internal refresh cycles that vary in response to on-chip temperature changes","assignee":null,"inventors":[],"filing_date":"2012-05-15T00:00:00.000Z","publication_date":"2013-09-17T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C"],"num_claims":9,"abstract":"An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memory refresh command signal received by the memory device. This change in the period of the internal memory refresh command may be in response to detecting a change in temperature of the memory device. In particular, the refresh control circuit is configured so that the period of the internal memory refresh command signal is increased in response to detecting a reduction in temperature of the memory device."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Methods of operating DRAM devices having adjustable internal refresh cycles that vary in response to on-chip temperature changes","description":"An integrated circuit memory device includes a refresh control circuit that generates an internal memory refresh command signal having a period that is changed relative to a period of an external memo","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8537633","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8537633","citation_suggestion":"Patentable. \"Methods of operating DRAM devices having adjustable internal refresh cycles that vary in response to on-chip temperature changes\" (US-8537633). https://patentable.app/patents/US-8537633","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8537633","json":"https://patentable.app/api/llm-context/US-8537633","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T21:55:58.091Z"}