{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8537634","patent":{"patent_number":"US-8537634","title":"Parallelized check pointing using MATs and through silicon VIAs (TSVs)","assignee":null,"inventors":[],"filing_date":"2009-11-13T00:00:00.000Z","publication_date":"2013-09-17T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C","G11C","H01L","H01L","H01L"],"num_claims":14,"abstract":"A system and method that includes a memory die, residing on a stacked memory, which is organized into a plurality of mats that include data. The system and method also includes an additional memory die, residing on the stacked memory, that is organized into an additional plurality of mats and connected to the memory die by a Through Silicon Vias (TSVs), the data to be transmitted along the TSVs."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Parallelized check pointing using MATs and through silicon VIAs (TSVs)","description":"A system and method that includes a memory die, residing on a stacked memory, which is organized into a plurality of mats that include data. The system and method also includes an additional memory di","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8537634","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8537634","citation_suggestion":"Patentable. \"Parallelized check pointing using MATs and through silicon VIAs (TSVs)\" (US-8537634). https://patentable.app/patents/US-8537634","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8537634","json":"https://patentable.app/api/llm-context/US-8537634","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T16:50:15.196Z"}