{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8537832","patent":{"patent_number":"US-8537832","title":"Exception detection and thread rescheduling in a multi-core, multi-thread network processor","assignee":null,"inventors":[],"filing_date":"2011-03-12T00:00:00.000Z","publication_date":"2013-09-17T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F"],"num_claims":14,"abstract":"Described embodiments provide a packet classifier of a network processor having a plurality of processing modules. A scheduler generates a thread of contexts for each tasks generated by the network processor corresponding to each received packet. The thread corresponds to an order of instructions applied to the corresponding packet. A multi-thread instruction engine processes the threads of instructions. A function bus interface inspects instructions received from the multi-thread instruction engine for one or more exception conditions. If the function bus interface detects an exception, the function bus interface reports the exception to the scheduler and the multi-thread instruction engine. The scheduler reschedules the thread corresponding to the instruction having the exception for processing in the multi-thread instruction engine. Otherwise, the function bus interface provides the instruction to a corresponding destination processing module of the network processor."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Exception detection and thread rescheduling in a multi-core, multi-thread network processor","description":"Described embodiments provide a packet classifier of a network processor having a plurality of processing modules. A scheduler generates a thread of contexts for each tasks generated by the network pr","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8537832","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8537832","citation_suggestion":"Patentable. \"Exception detection and thread rescheduling in a multi-core, multi-thread network processor\" (US-8537832). https://patentable.app/patents/US-8537832","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8537832","json":"https://patentable.app/api/llm-context/US-8537832","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T09:42:05.393Z"}