{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8539290","patent":{"patent_number":"US-8539290","title":"Isolation logic between non-volatile memory and test and wrapper controllers","assignee":null,"inventors":[],"filing_date":"2013-02-05T00:00:00.000Z","publication_date":"2013-09-17T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C"],"num_claims":5,"abstract":"An integrated circuit is described that has a substrate with a memory array with dedicated support hardware formed on the substrate. An access wrapper circuit is coupled to address and data lines of the memory array and to control lines of the dedicated support hardware. The wrapper circuit is configured to provide an access port to the memory array. A test controller is formed on the substrate and coupled in parallel with the access wrapper circuit to the address and data lines of the memory array and to the control lines of the dedicated support hardware, wherein the test controller is operable to perform a test of the memory array by manipulating control signals to the support hardware in addition to those required to write data patterns into the memory array and to read the contents of the memory array."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Isolation logic between non-volatile memory and test and wrapper controllers","description":"An integrated circuit is described that has a substrate with a memory array with dedicated support hardware formed on the substrate. An access wrapper circuit is coupled to address and data lines of t","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8539290","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8539290","citation_suggestion":"Patentable. \"Isolation logic between non-volatile memory and test and wrapper controllers\" (US-8539290). https://patentable.app/patents/US-8539290","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8539290","json":"https://patentable.app/api/llm-context/US-8539290","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T17:16:12.712Z"}