{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8541893","patent":{"patent_number":"US-8541893","title":"Semiconductor memory device and power line arrangement method thereof","assignee":null,"inventors":[],"filing_date":"2005-09-16T00:00:00.000Z","publication_date":"2013-09-24T00:00:00.000Z","cpc_codes":["H01L","H01L"],"num_claims":35,"abstract":"A semiconductor memory device and a power line arrangement method are disclosed. The semiconductor memory device includes a plurality of pads, each pad including an upper pad and a lower pad arranged below the upper pad, wherein pad power lines are arranged below the lower pads of the plurality of pads in a direction of crossing the pads to interconnect the pads that transmit the same level of electrical power among the plurality of pads."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Semiconductor memory device and power line arrangement method thereof","description":"A semiconductor memory device and a power line arrangement method are disclosed. The semiconductor memory device includes a plurality of pads, each pad including an upper pad and a lower pad arranged ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8541893","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8541893","citation_suggestion":"Patentable. \"Semiconductor memory device and power line arrangement method thereof\" (US-8541893). https://patentable.app/patents/US-8541893","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8541893","json":"https://patentable.app/api/llm-context/US-8541893","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T03:13:52.164Z"}