{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8542544","patent":{"patent_number":"US-8542544","title":"Semiconductor device having a plurality of memory regions and method of testing the same","assignee":null,"inventors":[],"filing_date":"2010-12-15T00:00:00.000Z","publication_date":"2013-09-24T00:00:00.000Z","cpc_codes":["G11C","G11C"],"num_claims":17,"abstract":"A semiconductor device may include, but is not limited to, first and second memory regions, and first to fifth control circuits. The first and second memory regions are mutually exclusive at the same time. The first control circuit performs a first access to the first memory region. The second control circuit performs a second access to the second memory region. The third control circuit controls activation and deactivation of the first and second control circuits based on a first logic received from a plurality of first external terminals. The fourth control circuit switches between the first and second accesses based on at least a second logic received from a second external terminal. The fifth control circuit controls validation and invalidation of the fourth control circuit."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Semiconductor device having a plurality of memory regions and method of testing the same","description":"A semiconductor device may include, but is not limited to, first and second memory regions, and first to fifth control circuits. The first and second memory regions are mutually exclusive at the same ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8542544","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8542544","citation_suggestion":"Patentable. \"Semiconductor device having a plurality of memory regions and method of testing the same\" (US-8542544). https://patentable.app/patents/US-8542544","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8542544","json":"https://patentable.app/api/llm-context/US-8542544","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T12:45:00.302Z"}