{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8543747","patent":{"patent_number":"US-8543747","title":"Delegating network processor operations to star topology serial bus interfaces","assignee":null,"inventors":[],"filing_date":"2011-10-04T00:00:00.000Z","publication_date":"2013-09-24T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","H04L","G06F"],"num_claims":21,"abstract":"An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. The data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. In one aspect of an embodiment of the invention, the messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Delegating network processor operations to star topology serial bus interfaces","description":"An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and co","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8543747","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8543747","citation_suggestion":"Patentable. \"Delegating network processor operations to star topology serial bus interfaces\" (US-8543747). https://patentable.app/patents/US-8543747","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8543747","json":"https://patentable.app/api/llm-context/US-8543747","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T09:56:27.027Z"}