{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-8543754","patent":{"patent_number":"US-8543754","title":"Low latency precedence ordering in a PCI express multiple root I/O virtualization environment","assignee":null,"inventors":[],"filing_date":"2011-02-25T00:00:00.000Z","publication_date":"2013-09-24T00:00:00.000Z","cpc_codes":["G06F","G06F"],"num_claims":24,"abstract":"An apparatus and method of low latency precedence ordering check in a PCI Express (PCIe) multiple root I/O virtualization (MR-IOV) environment. The precedence ordering check mechanism aids in enabling a port to comply with PCIe MR-IOV ordering rules. A posted information array mirrors a posted transaction queue, storing precedence order indicator and Virtual Hierarchy (VH) tag information for corresponding posted transaction entries stored in the posted transaction queue. The selector queries the posted information array periodically, such as each cycle, to determine whether the non-posted/completion transaction at the output of their respective queues have any preceding posted transactions of the same VH somewhere in the posted queue."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Low latency precedence ordering in a PCI express multiple root I/O virtualization environment","description":"An apparatus and method of low latency precedence ordering check in a PCI Express (PCIe) multiple root I/O virtualization (MR-IOV) environment. The precedence ordering check mechanism aids in enabling","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-8543754","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-8543754","citation_suggestion":"Patentable. \"Low latency precedence ordering in a PCI express multiple root I/O virtualization environment\" (US-8543754). https://patentable.app/patents/US-8543754","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-8543754","json":"https://patentable.app/api/llm-context/US-8543754","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T20:31:53.591Z"}