{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9588717","patent":{"patent_number":"US-9588717","title":"Fault-tolerance through silicon via interface and controlling method thereof","assignee":null,"inventors":[],"filing_date":"2014-12-19T00:00:00.000Z","publication_date":"2017-03-07T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G11C","G11C","G11C","H01L","H01L","H01L"],"num_claims":16,"abstract":"A fault-tolerance through silicon via (TSV) interface is disposed in a three-dimensional random access memory (3-D RAM) with N memory layers and M data access path sets, and each of the memory layers containing K memory arrays, and each of the data access path sets containing a plurality of TSV paths connecting to the memory layers. The fault-tolerance TSV interface includes a path controlling unit and a processing unit. The path controlling unit detects and controls the data access path sets. When a fault occurs in any data access path set connecting to a memory layer, the processing unit provides at least two different fault-tolerance access configurations. In each of the fault-tolerance access configurations, μ data access path sets are enabled to access all K memory arrays in the corresponding memory layer, where 0<μ