{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9589092","patent":{"patent_number":"US-9589092","title":"Method for co-designing flip-chip and interposer","assignee":null,"inventors":[],"filing_date":"2014-11-18T00:00:00.000Z","publication_date":"2017-03-07T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":16,"abstract":"A method for co-designing a flip-chip and an interposer is provided. Information regarding I/O pads, power pins and IR constraints of the flip-chip is obtained. A bump planning procedure is performed to obtain a total number of micro bumps of the flip-chip according to the information, and obtain a minimum conductance of each of the power pins of the flip-chip according to a bump placement of the micro bumps of the flip-chip. A chip-interposer routing procedure is performed to obtain a Re-Distribution Layer (RDL) routing of the flip-chip and an interposer routing of the interposer according to the minimum conductance of the power pins of the flip-chip."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method for co-designing flip-chip and interposer","description":"A method for co-designing a flip-chip and an interposer is provided. Information regarding I/O pads, power pins and IR constraints of the flip-chip is obtained. A bump planning procedure is performed ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9589092","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9589092","citation_suggestion":"Patentable. \"Method for co-designing flip-chip and interposer\" (US-9589092). https://patentable.app/patents/US-9589092","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9589092","json":"https://patentable.app/api/llm-context/US-9589092","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T05:00:16.892Z"}