{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9589660","patent":{"patent_number":"US-9589660","title":"Semiconductor pillars charged in read operation","assignee":null,"inventors":[],"filing_date":"2016-06-06T00:00:00.000Z","publication_date":"2017-03-07T00:00:00.000Z","cpc_codes":["G11C","G11C"],"num_claims":20,"abstract":"A memory device includes a word line above a semiconductor substrate, a semiconductor pillar extending through the word line in a direction crossing a surface of the semiconductor substrate, a memory cell at an intersection of the word line and the semiconductor pillar and having a gate electrically connected to the word line, a bit line electrically connected to a first end of the memory cell, a source line electrically connected to a second end of the memory cell, and a controller that controls a write operation on the memory cell, the write operation including a program operation followed by a verify operation. During the verify operation on the memory cell, the semiconductor pillar is charged after performing a read operation on the memory cell."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Semiconductor pillars charged in read operation","description":"A memory device includes a word line above a semiconductor substrate, a semiconductor pillar extending through the word line in a direction crossing a surface of the semiconductor substrate, a memory ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9589660","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9589660","citation_suggestion":"Patentable. \"Semiconductor pillars charged in read operation\" (US-9589660). https://patentable.app/patents/US-9589660","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9589660","json":"https://patentable.app/api/llm-context/US-9589660","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T12:27:13.909Z"}