{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9589811","patent":{"patent_number":"US-9589811","title":"FinFET spacer etch with no fin recess and no gate-spacer pull-down","assignee":null,"inventors":[],"filing_date":"2015-06-24T00:00:00.000Z","publication_date":"2017-03-07T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":16,"abstract":"A method may include providing a patterned feature extending from a substrate plane of a substrate, the patterned feature including a semiconductor portion and a coating in an unhardened state extending along a top region and along sidewall regions of the semiconductor portion; implanting first ions into the coating, the first ions having a first trajectory along a perpendicular to the substrate plane, wherein the first ions form a etch-hardened portion comprising a hardened state disposed along the top region; and directing a reactive etch using second ions at the coating, the second ions having a second trajectory forming a non-zero angle with respect to the perpendicular, wherein the reactive etch removes the etch-hardened portion at a first etch rate, wherein the first etch rate is less than a second etch rate when the second ions are directed in the reactive etch to the top portion in the unhardened state."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"FinFET spacer etch with no fin recess and no gate-spacer pull-down","description":"A method may include providing a patterned feature extending from a substrate plane of a substrate, the patterned feature including a semiconductor portion and a coating in an unhardened state extendi","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9589811","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9589811","citation_suggestion":"Patentable. \"FinFET spacer etch with no fin recess and no gate-spacer pull-down\" (US-9589811). https://patentable.app/patents/US-9589811","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9589811","json":"https://patentable.app/api/llm-context/US-9589811","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T04:31:27.472Z"}