{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9589936","patent":{"patent_number":"US-9589936","title":"3D integration of fanout wafer level packages","assignee":null,"inventors":[],"filing_date":"2015-02-10T00:00:00.000Z","publication_date":"2017-03-07T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":20,"abstract":"Fanout wafer level packages (FOWLPs) and methods of formation are described. In an embodiment, a package includes a first routing layer, a first die on a top side of the first routing layer, and a first molding compound encapsulating the first die on the first routing layer. A first plurality of conductive pillars extends from a bottom side of the first routing layer. A second die is on a top side of a second routing layer, and the first plurality of conductive pillars is on the top side of the routing layer. A second molding compound encapsulates the first molding compound, the first routing layer, the first plurality of conductive pillars, and the second die on the second routing layer. In an embodiment, a plurality of conductive bumps (e.g. solder balls) extends from a bottom side of the second routing layer."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"3D integration of fanout wafer level packages","description":"Fanout wafer level packages (FOWLPs) and methods of formation are described. In an embodiment, a package includes a first routing layer, a first die on a top side of the first routing layer, and a fir","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9589936","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9589936","citation_suggestion":"Patentable. \"3D integration of fanout wafer level packages\" (US-9589936). https://patentable.app/patents/US-9589936","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9589936","json":"https://patentable.app/api/llm-context/US-9589936","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T08:02:35.955Z"}