{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9594563","patent":{"patent_number":"US-9594563","title":"CPU archtecture with highly flexible allocation of execution resources to threads","assignee":null,"inventors":[],"filing_date":"2013-12-31T00:00:00.000Z","publication_date":"2017-03-14T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":20,"abstract":"A CPU architecture is proposed which flexibly allocates chip resources among threads. Execution units (microcores) are arranged in a ring. Instruction fetch units (front-ends) deposit instructions sequentially into storage elements within the microcores. Multiple front-ends can each feed segments of the ring; each such segment is a “smart queue”. If, due to a sustained higher execution rate, a thread catches up to the next thread ahead of it, the slower thread steps aside and lets the faster thread play through. Other circumstances may lead to a thread consuming more than its usual share of resources, possibly even all of the microcores, for a time. The architecture has no instruction set dependencies; it is applicable to existing instruction set architectures and will speed up execution of them significantly as compared to conventional architectures."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"CPU archtecture with highly flexible allocation of execution resources to threads","description":"A CPU architecture is proposed which flexibly allocates chip resources among threads. Execution units (microcores) are arranged in a ring. Instruction fetch units (front-ends) deposit instructions seq","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9594563","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9594563","citation_suggestion":"Patentable. \"CPU archtecture with highly flexible allocation of execution resources to threads\" (US-9594563). https://patentable.app/patents/US-9594563","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9594563","json":"https://patentable.app/api/llm-context/US-9594563","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T08:02:44.871Z"}