{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9594683","patent":{"patent_number":"US-9594683","title":"Data processing in a multiple processor system to maintain multiple processor cache memory access coherency","assignee":null,"inventors":[],"filing_date":"2014-11-17T00:00:00.000Z","publication_date":"2017-03-14T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F"],"num_claims":12,"abstract":"A data processing system including multiple processors with a hierarchical cache structure comprising multiple levels of cache between the processors and a main memory, wherein at least one page mover is positioned closer to the main memory and is connected to the cache memories of the at least one shared cache level (L2, L3, L4), the main memory and to the multiple processors to move data between the cache memories of the at least one shared cache level, the main memory and the processors. In response to a request from one of the processors, the at least one page mover fetches data of a storage area line-wise from at least one of the following memories: the cache memories and the main memory maintaining multiple processor cache memory access coherency."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Data processing in a multiple processor system to maintain multiple processor cache memory access coherency","description":"A data processing system including multiple processors with a hierarchical cache structure comprising multiple levels of cache between the processors and a main memory, wherein at least one page mover","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9594683","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9594683","citation_suggestion":"Patentable. \"Data processing in a multiple processor system to maintain multiple processor cache memory access coherency\" (US-9594683). https://patentable.app/patents/US-9594683","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9594683","json":"https://patentable.app/api/llm-context/US-9594683","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T12:31:47.836Z"}