{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9595319","patent":{"patent_number":"US-9595319","title":"Partial/full array/block erase for 2D/3D hierarchical NAND","assignee":null,"inventors":[],"filing_date":"2016-04-25T00:00:00.000Z","publication_date":"2017-03-14T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":59,"abstract":"A novel 2D/3D hierarchical-BL NAND array with at least one plane on independent Psubstrate comprising a plurality of LG groups respectively associated with a plurality of local bit lines (LBLs) laid at a level below a plurality of broken or non-broken global bit lines (GBLs) connected to Page Buffer. Each LG group includes multiple blocks and connects an independent power supply line to each of the plurality of LBLs. Each block including N-bit 2D/3D NAND strings each with S cells connected in series and terminated by two string-select devices and coupled to a common source line. In particular, random-size partial-block WLs are selected from each block of randomly selected LG groups of one plane of the 2D/3D NAND array for erase at the same time with border WLs being optionally preread and program into another plane of the 2D/3D NAND array or optionally saved off-chip and wrote back for data security."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Partial/full array/block erase for 2D/3D hierarchical NAND","description":"A novel 2D/3D hierarchical-BL NAND array with at least one plane on independent Psubstrate comprising a plurality of LG groups respectively associated with a plurality of local bit lines (LBLs) laid a","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9595319","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9595319","citation_suggestion":"Patentable. \"Partial/full array/block erase for 2D/3D hierarchical NAND\" (US-9595319). https://patentable.app/patents/US-9595319","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9595319","json":"https://patentable.app/api/llm-context/US-9595319","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T07:21:18.088Z"}