{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9595323","patent":{"patent_number":"US-9595323","title":"Word line compensation for memory arrays","assignee":null,"inventors":[],"filing_date":"2016-02-04T00:00:00.000Z","publication_date":"2017-03-14T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":20,"abstract":"A method is provided for operating a non-volatile storage system that includes a plurality of bit lines, a word line comb including a plurality of word lines, and a plurality of memory elements, each memory element coupled between one of the bit lines and one of the word lines. The method includes receiving a current conducted by the word line comb, estimating a resistance of a conductive path between the word line comb and a selected word line voltage node, and generating a voltage at the selected word line voltage node based on the received current and the estimated resistance so that a voltage of the word line comb substantially equals a reference voltage."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Word line compensation for memory arrays","description":"A method is provided for operating a non-volatile storage system that includes a plurality of bit lines, a word line comb including a plurality of word lines, and a plurality of memory elements, each ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9595323","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9595323","citation_suggestion":"Patentable. \"Word line compensation for memory arrays\" (US-9595323). https://patentable.app/patents/US-9595323","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9595323","json":"https://patentable.app/api/llm-context/US-9595323","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T08:40:27.111Z"}