{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9595450","patent":{"patent_number":"US-9595450","title":"Composite structure for gate level inter-layer dielectric","assignee":null,"inventors":[],"filing_date":"2013-12-26T00:00:00.000Z","publication_date":"2017-03-14T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L"],"num_claims":19,"abstract":"A method of forming an integrated circuit device includes forming dummy gates over a semiconductor substrate, depositing a first dielectric layer over the dummy gates, chemical mechanical polishing to recede the first dielectric layer to the height of the dummy gates, etching to recess the first dielectric layer below the height of the gates, depositing one or more additional dielectric layers over the first dielectric layer, and chemical mechanical polishing to recede the one or more additional dielectric layers to the height of the gates. The method provides integrated circuit devices having metal gate electrodes and an inter-level dielectric at the gate level that includes a capping layer. The capping layer resists etching and preserves the gate height through a replacement gate process."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Composite structure for gate level inter-layer dielectric","description":"A method of forming an integrated circuit device includes forming dummy gates over a semiconductor substrate, depositing a first dielectric layer over the dummy gates, chemical mechanical polishing to","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9595450","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9595450","citation_suggestion":"Patentable. \"Composite structure for gate level inter-layer dielectric\" (US-9595450). https://patentable.app/patents/US-9595450","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9595450","json":"https://patentable.app/api/llm-context/US-9595450","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T15:43:47.638Z"}