{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9595566","patent":{"patent_number":"US-9595566","title":"Floating staircase word lines and process in a 3D non-volatile memory having vertical bit lines","assignee":null,"inventors":[],"filing_date":"2015-02-25T00:00:00.000Z","publication_date":"2017-03-14T00:00:00.000Z","cpc_codes":["H01L","G11C","G11C","G11C","G11C","H01L","H01L","H01L","H01L","H01L"],"num_claims":20,"abstract":"A 3D nonvolatile memory has memory elements arranged in a three-dimensional pattern with a plurality of memory layers stacked over a semiconductor substrate. It has a 2D array of vertical bit lines and a plurality of staircase word lines. Each staircase word line has a series of alternating segments and risers and traverses the plurality of memory layers with a segment in each memory layer. The plurality of staircase word lines have their segments lined up to form a 2D array of stacks of segments. Riser for a pair of segments from each adjacent stacks at different memory layers is provided by a conductive sidewall layer of a stairwell disposed between the adjacent stacks. Multiple insulated conductive sidewall layers provide multiple risers for the adjacent stacks. Layer-by-layer stairwell excavation and sidewall processes between adjacent stacks create risers for different pairs of segments between stacks to form the staircase word lines."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Floating staircase word lines and process in a 3D non-volatile memory having vertical bit lines","description":"A 3D nonvolatile memory has memory elements arranged in a three-dimensional pattern with a plurality of memory layers stacked over a semiconductor substrate. It has a 2D array of vertical bit lines an","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9595566","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9595566","citation_suggestion":"Patentable. \"Floating staircase word lines and process in a 3D non-volatile memory having vertical bit lines\" (US-9595566). https://patentable.app/patents/US-9595566","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9595566","json":"https://patentable.app/api/llm-context/US-9595566","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T11:41:26.357Z"}