{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9595578","patent":{"patent_number":"US-9595578","title":"Undercut insulating regions for silicon-on-insulator device","assignee":null,"inventors":[],"filing_date":"2016-09-16T00:00:00.000Z","publication_date":"2017-03-14T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L"],"num_claims":8,"abstract":"A method of making a silicon-on-insulator (SOI) semiconductor device includes etching an undercut isolation trench into an SOI substrate, the SOI substrate comprising a bottom substrate, a buried oxide (BOX) layer formed on the bottom substrate, and a top SOI layer formed on the BOX layer, wherein the undercut isolation trench extends through the top SOI layer and the BOX layer and into the bottom substrate such that a portion of the undercut isolation trench is located in the bottom substrate underneath the BOX layer. The undercut isolation trench is filled with an undercut fill comprising an insulating material to form an undercut isolation region. A field effect transistor (FET) device is formed on the top SOI layer adjacent to the undercut isolation region, wherein the undercut isolation region extends underneath a source/drain region of the FET."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Undercut insulating regions for silicon-on-insulator device","description":"A method of making a silicon-on-insulator (SOI) semiconductor device includes etching an undercut isolation trench into an SOI substrate, the SOI substrate comprising a bottom substrate, a buried oxid","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9595578","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9595578","citation_suggestion":"Patentable. \"Undercut insulating regions for silicon-on-insulator device\" (US-9595578). https://patentable.app/patents/US-9595578","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9595578","json":"https://patentable.app/api/llm-context/US-9595578","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T04:15:12.447Z"}