{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9600018","patent":{"patent_number":"US-9600018","title":"Clock stoppage in integrated circuits with multiple asynchronous clock domains","assignee":null,"inventors":[],"filing_date":"2014-06-09T00:00:00.000Z","publication_date":"2017-03-21T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F"],"num_claims":16,"abstract":"Methods and circuits for performing a clock-stop process of a circuit are disclosed. For example, a circuit includes a clock group having a first clock domain, a first clock multiplexer, a first synchronizer and a controller. The controller is configured to initiate a clock stop process of the circuit by sending an alternative mode signal to the first synchronizer. The first synchronizer is configured to synchronize the alternative mode signal to a clock of the first clock domain and is further configured to output, to a select line of the first clock multiplexer, the alternative mode signal that is synchronized to the clock of the first clock domain. The select line of the first clock multiplexer is for selecting from between an input of the first clock multiplexer for the clock of the first clock domain and an alternative clock input of the first clock multiplexer for an alternative clock signal from the controller."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Clock stoppage in integrated circuits with multiple asynchronous clock domains","description":"Methods and circuits for performing a clock-stop process of a circuit are disclosed. For example, a circuit includes a clock group having a first clock domain, a first clock multiplexer, a first synch","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9600018","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9600018","citation_suggestion":"Patentable. \"Clock stoppage in integrated circuits with multiple asynchronous clock domains\" (US-9600018). https://patentable.app/patents/US-9600018","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9600018","json":"https://patentable.app/api/llm-context/US-9600018","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T05:42:03.849Z"}