{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9600024","patent":{"patent_number":"US-9600024","title":"Control method of clock gating for dithering in the clock signal to mitigate voltage transients","assignee":null,"inventors":[],"filing_date":"2013-09-25T00:00:00.000Z","publication_date":"2017-03-21T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F"],"num_claims":8,"abstract":"A control method for a clock signal for a CPU contained in a CMOS circuit includes: when a load current for the CMOS circuit is enabled, generating a first clock signal; in a first period, selectively gating certain cycles of the first clock signal to generate a second clock signal which has a clock rate less than a clock rate of the first clock signal; and in a second period, dithering in the gated cycles to increase the clock rate of the second clock signal to be equal to that of the first clock signal. The second clock signal is continuously input to the CMOS circuit during the first period and the second period."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Control method of clock gating for dithering in the clock signal to mitigate voltage transients","description":"A control method for a clock signal for a CPU contained in a CMOS circuit includes: when a load current for the CMOS circuit is enabled, generating a first clock signal; in a first period, selectively","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9600024","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9600024","citation_suggestion":"Patentable. \"Control method of clock gating for dithering in the clock signal to mitigate voltage transients\" (US-9600024). https://patentable.app/patents/US-9600024","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9600024","json":"https://patentable.app/api/llm-context/US-9600024","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T06:43:12.866Z"}