{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9601191","patent":{"patent_number":"US-9601191","title":"Exploiting phase-change memory write asymmetries to accelerate write","assignee":null,"inventors":[],"filing_date":"2013-12-20T00:00:00.000Z","publication_date":"2017-03-21T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C"],"num_claims":13,"abstract":"To improve the write performance of PCM, the disclosed technology, in certain embodiments, provides a new write scheme, referred to herein as two-stage-write, which leverages the speed and power asymmetries of writing a zero bit and a one bit. Writing a data block to PCM is divided into two separated stages, i.e., write-0 stage and write-1 stage. Without violating power constraints, during the write-0 stage, all zero bits in this data block are written to PCM at an accelerated speed; during the write-1 stage, all one bits are written to PCM, with more bits being written concurrently. In certain embodiments, the disclosed technology provides a new coding scheme to improve the speed of the write-1 stage by further increasing the number of bits that can be written to PCM in parallel."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Exploiting phase-change memory write asymmetries to accelerate write","description":"To improve the write performance of PCM, the disclosed technology, in certain embodiments, provides a new write scheme, referred to herein as two-stage-write, which leverages the speed and power asymm","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9601191","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9601191","citation_suggestion":"Patentable. \"Exploiting phase-change memory write asymmetries to accelerate write\" (US-9601191). https://patentable.app/patents/US-9601191","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9601191","json":"https://patentable.app/api/llm-context/US-9601191","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T07:03:36.413Z"}