{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9601217","patent":{"patent_number":"US-9601217","title":"Methods and circuitry for identifying logic regions affected by soft errors","assignee":null,"inventors":[],"filing_date":"2013-10-25T00:00:00.000Z","publication_date":"2017-03-21T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C"],"num_claims":20,"abstract":"Integrated circuits with single event upset (SEU) detection circuitry are provided. The SEU detection circuitry may include an error detection block for detecting soft errors and a sensitivity processor that determines whether or not to correct the detected soft errors. The sensitivity processor may be used to access a sensitivity map header (SMH) file that is stored on external memory. The sensitivity map header file contains information that can help identify which logic region on the integrated circuit the soft error affects and whether or not that soft error can critically cause functional failure for the integrated circuit. Depending on the criticality of the soft error, different corrective actions may be taken."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Methods and circuitry for identifying logic regions affected by soft errors","description":"Integrated circuits with single event upset (SEU) detection circuitry are provided. The SEU detection circuitry may include an error detection block for detecting soft errors and a sensitivity process","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9601217","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9601217","citation_suggestion":"Patentable. \"Methods and circuitry for identifying logic regions affected by soft errors\" (US-9601217). https://patentable.app/patents/US-9601217","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9601217","json":"https://patentable.app/api/llm-context/US-9601217","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T07:01:02.652Z"}