{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9602401","patent":{"patent_number":"US-9602401","title":"Technologies for high-speed PCS supporting FEC block synchronization with alignment markers","assignee":null,"inventors":[],"filing_date":"2014-12-23T00:00:00.000Z","publication_date":"2017-03-21T00:00:00.000Z","cpc_codes":["H04L","H04L","H04L","H04L","H04L","H04L"],"num_claims":19,"abstract":"Technologies for high-speed data transmission include a network port logic having one or more communication lanes coupled to a forward error correction (FEC) sublayer and a physical coding sublayer (PCS). To transmit data, the PCS encodes the data to be transmitted into encoded data blocks using a 66 b/64 b line code and inserts alignment marker blocks after every 16,383 encoded data blocks. The FEC encodes the encoded data blocks into 80-block FEC codewords starting at a predefined offset from an alignment marker. Thus, each alignment marker is at one of five predefined offsets from the beginning of an FEC codeword. Each alignment marker may include a unique block type field usable with FEC encoding. The PCS may include one or more logical lanes, each operating at 25 Gb/s. Embodiments of the network port logic may include a single PCS lane or sixteen PCS lanes. Other embodiments are described and claimed."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Technologies for high-speed PCS supporting FEC block synchronization with alignment markers","description":"Technologies for high-speed data transmission include a network port logic having one or more communication lanes coupled to a forward error correction (FEC) sublayer and a physical coding sublayer (P","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9602401","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9602401","citation_suggestion":"Patentable. \"Technologies for high-speed PCS supporting FEC block synchronization with alignment markers\" (US-9602401). https://patentable.app/patents/US-9602401","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9602401","json":"https://patentable.app/api/llm-context/US-9602401","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T05:33:55.704Z"}