{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9606608","patent":{"patent_number":"US-9606608","title":"Low power optimizations for a floating point multiplier","assignee":null,"inventors":[],"filing_date":"2014-03-19T00:00:00.000Z","publication_date":"2017-03-28T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F"],"num_claims":16,"abstract":"Systems and methods are described herein for reducing an amount of power consumption in a programmable integrated circuit device configured to perform a multiplication operation. The device includes a first multiplier that generates a first partial product associated with a first set of bit locations and a second multiplier that generates a second partial product associated with a second set of bit locations that are more significant than the first set of bit locations. The device further includes a switching circuitry to deactivate the first multiplier to reduce an amount of power consumed by the programmable integrated circuit device."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Low power optimizations for a floating point multiplier","description":"Systems and methods are described herein for reducing an amount of power consumption in a programmable integrated circuit device configured to perform a multiplication operation. The device includes a","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9606608","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9606608","citation_suggestion":"Patentable. \"Low power optimizations for a floating point multiplier\" (US-9606608). https://patentable.app/patents/US-9606608","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9606608","json":"https://patentable.app/api/llm-context/US-9606608","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T12:20:13.740Z"}