{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9606797","patent":{"patent_number":"US-9606797","title":"Compressing execution cycles for divergent execution in a single instruction multiple data (SIMD) processor","assignee":null,"inventors":[],"filing_date":"2012-12-21T00:00:00.000Z","publication_date":"2017-03-28T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":26,"abstract":"In one embodiment, the present invention includes a processor with a vector execution unit to execute a vector instruction on a vector having a plurality of individual data elements, where the vector instruction is of a first width and the vector execution unit is of a smaller width. The processor further includes a control logic coupled to the vector execution unit to compress a number of execution cycles consumed in execution of the vector instruction when at least some of the individual data elements are not to be operated on by the vector instruction. Other embodiments are described and claimed."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Compressing execution cycles for divergent execution in a single instruction multiple data (SIMD) processor","description":"In one embodiment, the present invention includes a processor with a vector execution unit to execute a vector instruction on a vector having a plurality of individual data elements, where the vector ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9606797","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9606797","citation_suggestion":"Patentable. \"Compressing execution cycles for divergent execution in a single instruction multiple data (SIMD) processor\" (US-9606797). https://patentable.app/patents/US-9606797","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9606797","json":"https://patentable.app/api/llm-context/US-9606797","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T10:12:02.690Z"}