{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9607117","patent":{"patent_number":"US-9607117","title":"Method and apparatus for calculating delay timing values for an integrated circuit design","assignee":null,"inventors":[],"filing_date":"2013-01-08T00:00:00.000Z","publication_date":"2017-03-28T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F"],"num_claims":13,"abstract":"A method of calculating at least one delay timing value for at least one setup timing stage within an integrated circuit design includes applying Negative/Positive Bias Temperature Instability (N/PBTI) compensation margins to delay values for elements within the at least one setup timing stage, and calculating the at least one delay timing value for the at least one setup timing stage based at least partly on the N/PBTI compensation margins applied to the delay values. The method further includes identifying at least partially equivalent elements within the parallel timing paths of the at least one setup timing stage, and applying reduced N/PBTI compensation margins to delay values for the identified at least partially equivalent elements within parallel timing paths of the at least one setup timing stage."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method and apparatus for calculating delay timing values for an integrated circuit design","description":"A method of calculating at least one delay timing value for at least one setup timing stage within an integrated circuit design includes applying Negative/Positive Bias Temperature Instability (N/PBTI","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9607117","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9607117","citation_suggestion":"Patentable. \"Method and apparatus for calculating delay timing values for an integrated circuit design\" (US-9607117). https://patentable.app/patents/US-9607117","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9607117","json":"https://patentable.app/api/llm-context/US-9607117","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T12:44:43.051Z"}