{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9607120","patent":{"patent_number":"US-9607120","title":"Implementing system irritator accelerator FPGA unit (AFU) residing behind a coherent attached processors interface (CAPI) unit","assignee":null,"inventors":[],"filing_date":"2014-12-30T00:00:00.000Z","publication_date":"2017-03-28T00:00:00.000Z","cpc_codes":["G06F"],"num_claims":11,"abstract":"A method and apparatus are provided for implementing system irritator accelerator field programmable gate array (FPGA) Units (AFUs) residing behind a Coherent Attached Processors Interface (CAPI) unit in a computer system. An AFU is implemented in an FPGA residing behind the CAPI unit, the AFU includes a system irritator accelerator. A processor configures the AFU and enables the AFU system irritator to execute. The AFU system irritator is replicated to create additional irritation and is re-programmable."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Implementing system irritator accelerator FPGA unit (AFU) residing behind a coherent attached processors interface (CAPI) unit","description":"A method and apparatus are provided for implementing system irritator accelerator field programmable gate array (FPGA) Units (AFUs) residing behind a Coherent Attached Processors Interface (CAPI) unit","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9607120","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9607120","citation_suggestion":"Patentable. \"Implementing system irritator accelerator FPGA unit (AFU) residing behind a coherent attached processors interface (CAPI) unit\" (US-9607120). https://patentable.app/patents/US-9607120","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9607120","json":"https://patentable.app/api/llm-context/US-9607120","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T06:41:27.433Z"}