{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9607702","patent":{"patent_number":"US-9607702","title":"Sub-block page erase in 3D p-channel flash memory","assignee":null,"inventors":[],"filing_date":"2015-03-25T00:00:00.000Z","publication_date":"2017-03-28T00:00:00.000Z","cpc_codes":["G11C","G11C"],"num_claims":19,"abstract":"A NAND array includes blocks of memory cells. A block of memory cells includes a plurality of strings having channel lines between first and second string select switches. The strings share a set of word lines between the first and second string select switches. A channel-side voltage can be applied to the channel lines. A control voltage can be applied to a selected subset of the first string select switches. The channel lines can be floated at ends of the second string select switches. Tunneling in memory cells coupled to an unselected subset of the first string select switches can be inhibited. Word line-side erase voltages can be applied to word lines in the set of word lines in the block to induce tunneling in memory cells coupled to the word lines and coupled to the selected subset of the first string select switches."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Sub-block page erase in 3D p-channel flash memory","description":"A NAND array includes blocks of memory cells. A block of memory cells includes a plurality of strings having channel lines between first and second string select switches. The strings share a set of w","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9607702","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9607702","citation_suggestion":"Patentable. \"Sub-block page erase in 3D p-channel flash memory\" (US-9607702). https://patentable.app/patents/US-9607702","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9607702","json":"https://patentable.app/api/llm-context/US-9607702","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T15:11:38.122Z"}