{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9607899","patent":{"patent_number":"US-9607899","title":"Integration of vertical transistors with 3D long channel transistors","assignee":null,"inventors":[],"filing_date":"2016-04-27T00:00:00.000Z","publication_date":"2017-03-28T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L"],"num_claims":20,"abstract":"A method for integrating a vertical transistor and a three-dimensional channel transistor includes forming narrow fins and wide fins in a substrate; forming a first source/drain (S/D) region at a base of the narrow fin and forming a gate dielectric layer and a gate conductor layer over the narrow fin and the wide fin. The gate conductor layer and the gate dielectric layer are patterned to form a vertical gate structure and a three-dimensional (3D) gate structure. Gate spacers are formed over sidewalls of the gate structures. A planarizing layer is deposited over the vertical gate structure and the 3D gate structure. A top portion of the narrow fin is exposed. S/D regions are formed on opposite sides of the 3D gate structure to form a 3D transistor, and a second S/D region is formed on the top portion of the narrow fin to form a vertical transistor."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Integration of vertical transistors with 3D long channel transistors","description":"A method for integrating a vertical transistor and a three-dimensional channel transistor includes forming narrow fins and wide fins in a substrate; forming a first source/drain (S/D) region at a base","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9607899","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9607899","citation_suggestion":"Patentable. \"Integration of vertical transistors with 3D long channel transistors\" (US-9607899). https://patentable.app/patents/US-9607899","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9607899","json":"https://patentable.app/api/llm-context/US-9607899","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T05:35:40.477Z"}