{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9612272","patent":{"patent_number":"US-9612272","title":"Testing memory devices with parallel processing operations","assignee":null,"inventors":[],"filing_date":"2014-02-26T00:00:00.000Z","publication_date":"2017-04-04T00:00:00.000Z","cpc_codes":["G11C"],"num_claims":20,"abstract":"An ATE system performs RA over NAND flash memory DUTs. A first UBM captures fresh failure related data from a DUT. A second UBM transmits existing failure related data. A fail engine accesses the stored existing failure related data and generates a failure list based thereon. The storing and the accessing the existing failure related data, and/or the generating the failure list, are performed in parallel contemporaneously in relation to the capturing the fresh data. The generated failure list is queued. A failure processor, which may be operable for controlling the capturing, computes a redundancy analysis based on the queued failure list. The first and second UBMs then ping-pong operably."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Testing memory devices with parallel processing operations","description":"An ATE system performs RA over NAND flash memory DUTs. A first UBM captures fresh failure related data from a DUT. A second UBM transmits existing failure related data. A fail engine accesses the stor","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9612272","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9612272","citation_suggestion":"Patentable. \"Testing memory devices with parallel processing operations\" (US-9612272). https://patentable.app/patents/US-9612272","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9612272","json":"https://patentable.app/api/llm-context/US-9612272","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T11:20:26.456Z"}