{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9613389","patent":{"patent_number":"US-9613389","title":"Method for hiding texture latency and managing registers on a processor","assignee":null,"inventors":[],"filing_date":"2011-12-14T00:00:00.000Z","publication_date":"2017-04-04T00:00:00.000Z","cpc_codes":["G06T","G06F","G06F"],"num_claims":3,"abstract":"A method for hiding texture latency in a multi-thread virtual pipeline (MVP) processor including the steps of: allowing the MVP processor to start running a main rendering program; segmenting registers of various MVP kernel instances in the MVP processor according to the length set, acquiring a plurality of register sets with the same length, binding the register sets to chipsets of the processor at the beginning of the running of the kernel instance; allowing a shader thread to give up a processing time slot occupied by the shader thread after sending a texture detail request, and setting a Program Counter (PC) value in the case of return; and returning texture detail and allowing the shader thread to restart running."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method for hiding texture latency and managing registers on a processor","description":"A method for hiding texture latency in a multi-thread virtual pipeline (MVP) processor including the steps of: allowing the MVP processor to start running a main rendering program; segmenting register","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9613389","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9613389","citation_suggestion":"Patentable. \"Method for hiding texture latency and managing registers on a processor\" (US-9613389). https://patentable.app/patents/US-9613389","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9613389","json":"https://patentable.app/api/llm-context/US-9613389","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T07:32:51.706Z"}