{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9613704","patent":{"patent_number":"US-9613704","title":"2D/3D NAND memory array with bit-line hierarchical structure for multi-page concurrent SLC/MLC program and program-verify","assignee":null,"inventors":[],"filing_date":"2014-12-25T00:00:00.000Z","publication_date":"2017-04-04T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":124,"abstract":"This invention discloses 2D or 3D NAND flash array in two-level BL-hierarchical structure with flexible multi-page or random-page-based concurrent, mixed SLC and MLC Read, Program or Program-Verify operations including bit-flipping for each program state or any combinations of above operations. Tracking techniques of self-timed control and algorithm of programming, read and local-bit line (LBL) voltage generations are proposed for enhancing automatic controls over charging and discharging of a plurality of WLs and LBLs in one or more randomly selected Blocks in one or more Segments of one or more Groups in a NAND plane for m-page concurrent operations using Vdd/Vss to Vinh/Vss Program page data conversion, multiple pseudo CACHEs based on LBL capacitors for storing raw SLC and MSB/LSB loaded page data, writing back or reading from Sense-Amplifier, Program/Read Buffer, real CHCHE, and multiple pseudo CACHEs with M-fold reduction in latency and power consumption."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"2D/3D NAND memory array with bit-line hierarchical structure for multi-page concurrent SLC/MLC program and program-verify","description":"This invention discloses 2D or 3D NAND flash array in two-level BL-hierarchical structure with flexible multi-page or random-page-based concurrent, mixed SLC and MLC Read, Program or Program-Verify op","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9613704","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9613704","citation_suggestion":"Patentable. \"2D/3D NAND memory array with bit-line hierarchical structure for multi-page concurrent SLC/MLC program and program-verify\" (US-9613704). https://patentable.app/patents/US-9613704","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9613704","json":"https://patentable.app/api/llm-context/US-9613704","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T12:46:55.279Z"}