{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9613844","patent":{"patent_number":"US-9613844","title":"3D semiconductor device having two layers of transistors","assignee":null,"inventors":[],"filing_date":"2015-08-07T00:00:00.000Z","publication_date":"2017-04-04T00:00:00.000Z","cpc_codes":["H01L","G11C","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":6,"abstract":"A 3D semiconductor device, including: a first layer including first transistors; a first interconnection layer interconnecting the first transistors and overlying the first layer; and a second layer including second transistors, where the second layer thickness is less than 2 microns and greater than 5 nm, where the second layer is overlying the first interconnection layer, and where the second layer includes dice lines formed by an etch step."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"3D semiconductor device having two layers of transistors","description":"A 3D semiconductor device, including: a first layer including first transistors; a first interconnection layer interconnecting the first transistors and overlying the first layer; and a second layer i","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9613844","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9613844","citation_suggestion":"Patentable. \"3D semiconductor device having two layers of transistors\" (US-9613844). https://patentable.app/patents/US-9613844","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9613844","json":"https://patentable.app/api/llm-context/US-9613844","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T17:27:12.967Z"}