{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9619393","patent":{"patent_number":"US-9619393","title":"Optimized use of hardware micro partition prefetch based on software thread usage","assignee":null,"inventors":[],"filing_date":"2015-11-09T00:00:00.000Z","publication_date":"2017-04-11T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":10,"abstract":"A system and/or computer program product selectively adjusts a resources addresses cache of addresses of resources used by virtual processors. A first dispatch from a hypervisor dispatches a first virtual processor, and then tracks processes executed by the first virtual processor. The hypervisor caches cache addresses of resources used by the processes after the first dispatch in a resources addresses cache. The hypervisor undispatches the first virtual processor, and then redispatches the first virtual processor as a second virtual processor by issuing a second dispatch. Processes executed by the second virtual processor are compared to processes executed during by the first virtual processor, thus leading to an identification of a level of process utilization consistency. The hypervisor then adjusts the resources addresses cache by selectively clearing resource addresses based on the level of process utilization consistency."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Optimized use of hardware micro partition prefetch based on software thread usage","description":"A system and/or computer program product selectively adjusts a resources addresses cache of addresses of resources used by virtual processors. A first dispatch from a hypervisor dispatches a first vir","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9619393","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9619393","citation_suggestion":"Patentable. \"Optimized use of hardware micro partition prefetch based on software thread usage\" (US-9619393). https://patentable.app/patents/US-9619393","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9619393","json":"https://patentable.app/api/llm-context/US-9619393","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T07:26:54.868Z"}