{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9620193","patent":{"patent_number":"US-9620193","title":"Semiconductor memory devices, memory systems including refresh control circuit and method of performing weak refresh operation on the weak pages thereof","assignee":null,"inventors":[],"filing_date":"2015-07-08T00:00:00.000Z","publication_date":"2017-04-11T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C"],"num_claims":18,"abstract":"A semiconductor memory device includes a memory cell array and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The refresh control circuit performs a normal refresh operation on the plurality of memory cell rows and performs a weak refresh operation on a plurality of weak pages of the plurality of memory cell rows. Each of the weak pages includes at least one weak cell whose data retention time is smaller than normal cells. The refresh control circuit transmits a refresh flag signal to a memory controller external to the semiconductor memory device when the refresh control circuit performs the weak refresh operation on the weak pages in a normal access mode."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Semiconductor memory devices, memory systems including refresh control circuit and method of performing weak refresh operation on the weak pages thereof","description":"A semiconductor memory device includes a memory cell array and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The refresh control circuit performs a normal ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9620193","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9620193","citation_suggestion":"Patentable. \"Semiconductor memory devices, memory systems including refresh control circuit and method of performing weak refresh operation on the weak pages thereof\" (US-9620193). https://patentable.app/patents/US-9620193","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9620193","json":"https://patentable.app/api/llm-context/US-9620193","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T17:45:22.145Z"}