{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9620202","patent":{"patent_number":"US-9620202","title":"Reduction or elimination of a latency penalty associated with adjusting read thresholds for non-volatile memory","assignee":null,"inventors":[],"filing_date":"2013-11-22T00:00:00.000Z","publication_date":"2017-04-11T00:00:00.000Z","cpc_codes":["G11C","G06F","G06F","G06F","G06F","G06F","G06F","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":35,"abstract":"Channel information and channel conditions that are determined by an Offline Tracking process are used to determine whether or not an adjustment to the read reference voltage can be avoided altogether without detrimentally affecting performance, or, alternatively, to determine a precision with which a read reference voltage adjustment should be made. If it is determined based on the channel conditions that a read reference voltage adjustment can be avoided altogether, read performance is improved by reducing the probability that a read reference voltage adjustment needs to be made during normal read operations. If it is determined based on the channel conditions that a read reference voltage adjustment needs to be made with a particular precision, the read reference voltage is adjusted with that precision. This latter approach is advantageous in that a determination that the precision with which the adjustments can be made is relatively low leads to fewer adjustments having to be made during normal read operations."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Reduction or elimination of a latency penalty associated with adjusting read thresholds for non-volatile memory","description":"Channel information and channel conditions that are determined by an Offline Tracking process are used to determine whether or not an adjustment to the read reference voltage can be avoided altogether","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9620202","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9620202","citation_suggestion":"Patentable. \"Reduction or elimination of a latency penalty associated with adjusting read thresholds for non-volatile memory\" (US-9620202). https://patentable.app/patents/US-9620202","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9620202","json":"https://patentable.app/api/llm-context/US-9620202","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T04:09:06.963Z"}