{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9620204","patent":{"patent_number":"US-9620204","title":"Interconnection architecture for multilayer circuits","assignee":null,"inventors":[],"filing_date":"2013-01-18T00:00:00.000Z","publication_date":"2017-04-11T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":9,"abstract":"A computer readable memory includes a circuit layer, a multilayer memory stacked over the circuit layer to form a memory box, the memory box comprising a bottom surface interfacing with the circuit layer and four side surfaces, and a first switching crossbar array disposed on a first side of the memory box. A plurality of vias connects the circuit layer to the first switching crossbar layer. The first switching crossbar array accepts signals from the plurality of vias and selectively connects a crossbar in the multilayer memory to the circuit layer. A method for addressing multilayer memory is also provided."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Interconnection architecture for multilayer circuits","description":"A computer readable memory includes a circuit layer, a multilayer memory stacked over the circuit layer to form a memory box, the memory box comprising a bottom surface interfacing with the circuit la","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9620204","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9620204","citation_suggestion":"Patentable. \"Interconnection architecture for multilayer circuits\" (US-9620204). https://patentable.app/patents/US-9620204","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9620204","json":"https://patentable.app/api/llm-context/US-9620204","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T05:39:04.109Z"}