{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9620246","patent":{"patent_number":"US-9620246","title":"Operating method of memory system","assignee":null,"inventors":[],"filing_date":"2015-05-14T00:00:00.000Z","publication_date":"2017-04-11T00:00:00.000Z","cpc_codes":["G11C","G06F","G11C","G11C"],"num_claims":16,"abstract":"Second data is generated by re-reading first data using a second read voltage when a first ECC decoding to first data using a first read voltage fails. Third data is generated by performing a second ECC decoding to the second data. An error-bit-number, which is a number of bits different between the second data and the third data, is obtained when the second ECC decoding fails. The process is repeated by changing the second read voltage until the error-bit-number is smaller than a predetermined threshold value. A third ECC decoding is performed to an optimal data that is the second data read using the second read voltage, with which the error-bit-number is smaller than the predetermined threshold value."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Operating method of memory system","description":"Second data is generated by re-reading first data using a second read voltage when a first ECC decoding to first data using a first read voltage fails. Third data is generated by performing a second E","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9620246","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9620246","citation_suggestion":"Patentable. \"Operating method of memory system\" (US-9620246). https://patentable.app/patents/US-9620246","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9620246","json":"https://patentable.app/api/llm-context/US-9620246","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T11:45:10.735Z"}