{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9620380","patent":{"patent_number":"US-9620380","title":"Methods for fabricating integrated circuits using self-aligned quadruple patterning","assignee":null,"inventors":[],"filing_date":"2015-12-17T00:00:00.000Z","publication_date":"2017-04-11T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L"],"num_claims":18,"abstract":"A method for fabricating an integrated circuit includes providing an semiconductor wafer includes forming in an upper mandrel layer a first upper mandrel having a first critical dimension and a second upper mandrel having a second critical dimension; forming upper sidewall spacers along sidewalls of the first upper mandrel while leaving the second upper mandrel without sidewall spacers; removing the first upper mandrel from between the upper sidewall spacers; transferring a pattern of the upper sidewall spacers and of the second upper mandrel into a lower mandrel layer to form first lower mandrels according to the pattern of the upper sidewall spacers and a second lower mandrel according to the pattern of the second upper mandrel; and forming lower sidewall spacers along sidewalls of the first and second lower mandrels."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Methods for fabricating integrated circuits using self-aligned quadruple patterning","description":"A method for fabricating an integrated circuit includes providing an semiconductor wafer includes forming in an upper mandrel layer a first upper mandrel having a first critical dimension and a second","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9620380","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9620380","citation_suggestion":"Patentable. \"Methods for fabricating integrated circuits using self-aligned quadruple patterning\" (US-9620380). https://patentable.app/patents/US-9620380","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9620380","json":"https://patentable.app/api/llm-context/US-9620380","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T11:18:16.258Z"}