{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9620493","patent":{"patent_number":"US-9620493","title":"Method of manufacturing three-dimensional semiconductor chip","assignee":null,"inventors":[],"filing_date":"2015-06-23T00:00:00.000Z","publication_date":"2017-04-11T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":8,"abstract":"A method of manufacturing a three-dimensional (3D) semiconductor includes dividing each of a plurality of wafers into a plurality of multi-dies each including a plurality of dies; checking whether each of the dies has a defect; storing a result of checking whether each of the dies has a defect and information regarding each of the multi-dies; forming virtual combined structures by combining and stacking all the multi-dies in a predetermined number of layers; forming 3D semiconductor groups by calculating yields of the combined structures based on the result of checking whether each of the dies has a defect and the information regarding each of the multi-dies, selecting a combined structure having a highest yield from among the combined structures, and stacking the multi-dies to have the same structure as the selected combined structure; and forming a 3D semiconductor chip by dividing the 3D semiconductor groups in units of dies."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method of manufacturing three-dimensional semiconductor chip","description":"A method of manufacturing a three-dimensional (3D) semiconductor includes dividing each of a plurality of wafers into a plurality of multi-dies each including a plurality of dies; checking whether eac","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9620493","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9620493","citation_suggestion":"Patentable. \"Method of manufacturing three-dimensional semiconductor chip\" (US-9620493). https://patentable.app/patents/US-9620493","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9620493","json":"https://patentable.app/api/llm-context/US-9620493","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T06:43:24.701Z"}