{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9620497","patent":{"patent_number":"US-9620497","title":"Structure and method for dynamic biasing to improve ESD robustness of current mode logic (CML) drivers","assignee":null,"inventors":[],"filing_date":"2015-08-17T00:00:00.000Z","publication_date":"2017-04-11T00:00:00.000Z","cpc_codes":["G06F"],"num_claims":6,"abstract":"An integrated circuit having a CML driver including a driver biasing network. A first output pad and a second output pad are connected to a voltage pad. A first driver is connected to the first output pad and the voltage pad. A second driver is connected to the second output pad and the voltage pad. A first ESD circuit is connected to the voltage pad, the first output pad, and the first driver. A second ESD circuit is connected to the voltage pad, the second output pad, and the second driver. The first ESD circuit biases the first driver toward a voltage of the voltage pad when an ESD event occurs at the first output pad, and the second ESD circuit biases the second driver toward the voltage of the voltage pad when an ESD event occurs at the second output pad."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Structure and method for dynamic biasing to improve ESD robustness of current mode logic (CML) drivers","description":"An integrated circuit having a CML driver including a driver biasing network. A first output pad and a second output pad are connected to a voltage pad. A first driver is connected to the first output","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9620497","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9620497","citation_suggestion":"Patentable. \"Structure and method for dynamic biasing to improve ESD robustness of current mode logic (CML) drivers\" (US-9620497). https://patentable.app/patents/US-9620497","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9620497","json":"https://patentable.app/api/llm-context/US-9620497","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T06:45:40.303Z"}