{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9626294","patent":{"patent_number":"US-9626294","title":"Performance-driven cache line memory access","assignee":null,"inventors":[],"filing_date":"2012-10-03T00:00:00.000Z","publication_date":"2017-04-18T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F"],"num_claims":11,"abstract":"According to one aspect of the present disclosure a system and technique for performance-driven cache line memory access is disclosed. The system includes: a processor, a cache hierarchy coupled to the processor, and a memory coupled to the cache hierarchy. The system also includes logic executable to, responsive to receiving, a request for a cache line: divide the request into a plurality of cache subline requests, wherein at least one of the cache subline requests comprises a high priority data request and at least one of the cache subline requests comprises a low priority data request; service the high priority data request; and delay servicing of the low priority data request until a low priority condition has been satisfied."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Performance-driven cache line memory access","description":"According to one aspect of the present disclosure a system and technique for performance-driven cache line memory access is disclosed. The system includes: a processor, a cache hierarchy coupled to th","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9626294","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9626294","citation_suggestion":"Patentable. \"Performance-driven cache line memory access\" (US-9626294). https://patentable.app/patents/US-9626294","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9626294","json":"https://patentable.app/api/llm-context/US-9626294","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T05:16:27.643Z"}