{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9627019","patent":{"patent_number":"US-9627019","title":"High speed FPGA boot-up through concurrent multi-frame configuration scheme","assignee":null,"inventors":[],"filing_date":"2016-06-29T00:00:00.000Z","publication_date":"2017-04-18T00:00:00.000Z","cpc_codes":["G11C","G06F","G11C","G11C"],"num_claims":20,"abstract":"Systems and methods are provided herein for implementing a programmable integrated circuit device that enables high-speed FPGA boot-up through a significant reduction of configuration time. By enabling high-speed FPGA boot-up, the programmable integrated circuit device will be able to accommodate applications that require faster boot-up time than conventional programmable integrated circuit devices are able to accommodate. In order to enable high-speed boot-up, dedicated address registers are implemented for each data line segment of a data line, which in turn significantly reduces configuration random access memory (CRAM) write time (e.g., by a factor of at least two)."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"High speed FPGA boot-up through concurrent multi-frame configuration scheme","description":"Systems and methods are provided herein for implementing a programmable integrated circuit device that enables high-speed FPGA boot-up through a significant reduction of configuration time. By enablin","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9627019","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9627019","citation_suggestion":"Patentable. \"High speed FPGA boot-up through concurrent multi-frame configuration scheme\" (US-9627019). https://patentable.app/patents/US-9627019","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9627019","json":"https://patentable.app/api/llm-context/US-9627019","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T12:36:20.275Z"}