{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9628055","patent":{"patent_number":"US-9628055","title":"SR latch circuit with single gate delay","assignee":null,"inventors":[],"filing_date":"2015-09-24T00:00:00.000Z","publication_date":"2017-04-18T00:00:00.000Z","cpc_codes":["H04B","H04L","H04L"],"num_claims":20,"abstract":"An SR latch circuit with single gate delay is provided. The circuit has an enable input and an SR latch. There is first input stage having an input for receiving a set input and having an output for producing a first component of the SR latch circuit output, the first input stage having only one transistor that receives the enable input, the first input stage becoming transparent while enabled, the first input stage having a single gate delay between the input of the first input stage and the output of the first input stage. There is a second input stage having an input for receiving a reset input and having an output for producing a second component of the SR latch circuit output, the second input stage having only one transistor that receives the enable input, the second input stage becoming transparent while enabled, the second input stage having a single gate delay between the input of the second input stage and the output of the second input stage."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"SR latch circuit with single gate delay","description":"An SR latch circuit with single gate delay is provided. The circuit has an enable input and an SR latch. There is first input stage having an input for receiving a set input and having an output for p","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9628055","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9628055","citation_suggestion":"Patentable. \"SR latch circuit with single gate delay\" (US-9628055). https://patentable.app/patents/US-9628055","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9628055","json":"https://patentable.app/api/llm-context/US-9628055","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T06:40:18.534Z"}