{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-9632954","patent":{"patent_number":"US-9632954","title":"Memory queue handling techniques for reducing impact of high-latency memory operations","assignee":null,"inventors":[],"filing_date":"2011-11-07T00:00:00.000Z","publication_date":"2017-04-25T00:00:00.000Z","cpc_codes":["G06F","G06F"],"num_claims":28,"abstract":"Techniques for handling queuing of memory accesses prevent passing excessive requests that implicate a region of memory subject to a high latency memory operation, such as a memory refresh operation, memory scrubbing or an internal bus calibration event, to a re-order queue of a memory controller. The memory controller includes a queue for storing pending memory access requests, a re-order queue for receiving the requests, and a control logic implementing a queue controller that determines if there is a collision between a received request and an ongoing high-latency memory operation. If there is a collision, then transfer of the request to the re-order queue may be rejected outright, or a count of existing queued operations that collide with the high latency operation may be used to determine if queuing the new request will exceed a threshold number of such operations."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory queue handling techniques for reducing impact of high-latency memory operations","description":"Techniques for handling queuing of memory accesses prevent passing excessive requests that implicate a region of memory subject to a high latency memory operation, such as a memory refresh operation, ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-9632954","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-9632954","citation_suggestion":"Patentable. \"Memory queue handling techniques for reducing impact of high-latency memory operations\" (US-9632954). https://patentable.app/patents/US-9632954","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-9632954","json":"https://patentable.app/api/llm-context/US-9632954","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-06-06T12:34:48.625Z"}